The technology described herein relates to graphics processors, and in particular to the mapping of threads to registers when executing graphics shader programs.
Graphics processing is typically carried out in a pipelined fashion, with one or more pipeline stages operating on the data to generate the final render output, e.g. frame that is displayed. Many graphics processing pipelines now include one or more programmable processing stages, commonly referred to as “shaders”. For example, a graphics processing pipeline may include one or more of, and typically all of, a geometry shader, a vertex shader and a fragment (pixel) shader. These shaders are programmable processing stages that execute shader programs on input data values to generate a desired set of output data (e.g. appropriately shaded and rendered fragment data in the case of a fragment shader) for processing by the rest of the graphics pipeline and/or for output. The shaders of the graphics processing pipeline may share programmable processing circuitry, or they may each be distinct programmable processing units.
A graphics processing unit (GPU) shader core is thus a processing unit that performs graphics processing by running small programs for each graphics item in a graphics output to be generated, such as a render target, e.g. frame (an “item” in this regard is usually a vertex or a sampling position (e.g. in the case of a fragment shader)). This generally enables a high degree of parallelism, in that a typical render output, e.g. frame, features a rather large number of vertices and fragments, each of which can be processed independently.
In graphics shader operation, each “item” will be processed by means of an execution thread which will execute the shader program in question for the graphics “item” in question.
A graphics shader program that is executed by a shading stage of a graphics processing pipeline will typically perform a sequence of instructions that read data from and write data to respective registers. Each execution thread for which the shader program is executed will typically have an allocated register or set of registers that it will read and write its respective data to and from. The registers for this purpose will typically be organised into one or more banks of registers, and respective threads will be allocated registers from a respective bank or banks of the register banks for their use.
Typically there will be a predefined register file mapping that will map the registers in the register bank or banks to respective execution threads, and the execution threads will then use the registers that they have been allocated according to the register file mapping when they execute the shader program in question.
The Applicants believe that there remains scope for improvements to the mapping of execution threads to registers when executing shader programs in graphics processing systems.
Like reference numerals are used for like components where appropriate in the drawings.